chip-design-mcp

sandraschi/chip-design-mcp

★ 0 stars Python File System Updated today

MCP server + React webapp for open-source chip design: write hardware in Verilog (RTL), run simulation and Yosys synthesis, optional OpenLane place-and-route to GDSII layout files (sky130 PDK). MCP/REST :11022, dashboard :11023.

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Quick Install

Copy the config for your editor. Some servers may need additional setup — check the README.

Add to claude_desktop_config.json:

{
  "mcpServers": {
    "chip-design-mcp": {
      "command": "uvx",
      "args": [
        "chip-design-mcp"
      ]
    }
  }
}

Or install with pip: pip install chip-design-mcp

README Excerpt

**A superyacht magazine for custom silicon** — browse the open RTL→GDSII world, run real tools if you insist, and maybe one day solder a package onto a **KiCad** board you also designed. The fascinating bit: much of this is **actually possible** without a nine-figure NRE line item. It is still hard, hot, slow, and easy to get wrong.

chip-design-mcp

Quick Install

README Excerpt

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